1. Field of the Invention
The invention relates to scaling video, and more particularly, to a method and apparatus for performing frame synchronization between incoming video signals and outgoing video signals when scaling video.
2. Description of the Prior Art
Display units are often used to receive and display image frames contained in a video signal received on a serial communication channel. As commonly referenced, display units include both analog display units (typically based on cathode ray tube technology) and digital display units (typically based on flat panels). As is well known, the image frames are represented by pixel data elements encoded within a display data portion of the video signal.
Video signals generally also contain synchronization signals that indicate the transitions between the line boundaries and frame boundaries in the accompanying display data. Examples of such signals include the horizontal synchronization HSYNC signal (indicating a transition to a next line) and the vertical synchronization VSYNC signal (indicating a transition from a current frame to a next frame), as is well known in the relevant arts.
When scaling image frames from a first resolution to a second resolution, conventionally generate outgoing frames at the second resolution at the same rate as the incoming frames are received. That is, in a scaling apparatus, each incoming frame results in an outgoing frame with a precise timing relationship. The method of locking the incoming frame rate to the outgoing frame rate is commonly referred to as frame synchronization. When frame lock is achieved, vertical synchronization VSYNC signals (i.e., frames) in the outgoing video signals are separated by the same time period as the vertical synchronization VSYNC signals in the incoming video signals.
FIG. 1 shows a block diagram of a typical video scaling apparatus 100. The video scaling apparatus 100 includes a receiver 102, a scaler 104, a transmitter 106, a clock generator 110, and an oscillator 114. The receiver 102 receives an incoming video signal Video_in and extracts incoming pixel data Pixel_in, a vertical sync signal VS_in, and a horizontal sync signal HS_in. The clock generator 110 generates an output clock Clk_out according to the output of the oscillator 114 such that during an outgoing frame time as determined by the incoming frame time, the correct number of lines and pixels in each line can be transmitted in the outgoing video signals. The scaler 104 generates outgoing video signals comprising outgoing pixel data Pixel_out, an outgoing vertical sync signal VS_out, and an outgoing horizontal sync signal HS_out according to the incoming information Pixel_in, VS_in, HS_in, the output clock Clk_out, and the desired second resolution. The transmitter 106 converts the generated video signals Pixel_out, VS_out, HS_out into an outgoing video signal Video_out for transmission to a display unit (not shown).
FIG. 2 shows a timing diagram of synchronization signals VS_out, HS_out corresponding to frames and lines in the outgoing video signals (Pixel_out, VS_out, HS_out) generated by the scaler 104. Within each frame, rising edges in the horizontal synchronization signal HS_out are used to determine the starting position of specific pixel data elements that represent lines of the image frame. Among the many pixel data elements contained in the pixel data Pixel_out, some pixel data elements correspond to the displayed image frame and others correspond to the non-display period. In many known display units, signals are generated based on the synchronization signals to indicate whether an active horizontal line and active pixel data element are presently being received. The active pixels in the active lines represent image to be displayed while non-active pixel data can be used to transmit other data such as control information. The Line_out variable shown in FIG. 2 indicates the outgoing line number for each horizontal line in the outgoing frame. For example, in a 1024×768 XGA signal, there are typically 768 active lines having 1024 active pixels in display signal. Additionally, there are approximately 38 non-active lines in each frame present when the vertical sync signal VS_out is not asserted. Therefore, the total number of lines n in each frame for this example would be n=806.
However, a problem exists when attempting to lock the incoming frame rate to the outgoing frame rate. In particular, unless the outgoing clock signal Clk_out is generated exactly at the correct frequency, there will always some leftover space at the end of the frame which will result in a partial line, indicated as the (n+1)th line 202 in FIG. 2. The reason for the partial line 202 is that it is not normally possible to have the exact desired frequency of the output Clk_out so the next incoming frame will start immediately after a last line in the current outgoing frame is fully completed. Additionally, electro magnetic interference (EMI) reduction techniques such as spread-spectrum clock signals or other factors such as operating temperature or device manufacturing impurities may cause the outgoing clock Clk_out to deviate from the exact desired frequency.